The cold cathode fluorescent lamp (CCFL) has come into widespread use as a back light source for products such as a liquid crystal monitor of a notebook PC, a liquid crystal display, and so on. In general, the CCFL might be of higher efficiency and longer life use than those of an ordinary hot cathode fluorescent lamp. A filament usually provided in a hot cathode fluorescent lamp is omitted from the CCFL.
Start-up and activation of the CCFL require a high AC voltage. For instance, a start-up voltage of the CCFL is about 1,000 volts, and an operating voltage of the CCFL is about 600 volts. Such a high AC voltage is produced from a DC power source of a laptop computer or a liquid crystal display through use of a DC-AC converter, or an inverter.
Referring to FIG. 3, a typical DC-AC converter 10 includes a pulse width modulator (PWM) 110, a driving circuit 120, and a transformation circuit 130.
The PWM 110 includes a first pulse output 111, a second pulse output 112, a third pulse output 113, and a fourth pulse output 114, all of which can provide sequential pulse signals.
The driving circuit 120 includes a direct current input 125, a first switching unit 121, a second switching unit 122, a third switching unit 123, and a fourth switching unit 124. The first switching unit 121 includes a first P-type transistor 1211 and a first N-type transistor 1212. The second switching unit 122 includes a second P-type transistor 1221 and a second N-type transistor 1222. The third switching unit 123 includes a third P-type transistor 1231 and a third N-type transistor 1232. The fourth switching unit 124 includes a fourth P-type transistor 1241 and a fourth N-type transistor 1242.
The transformation circuit 130 includes a first transformer 131, a second transformer 132, a first capacitor 133, and a second capacitor 134. The first transformer 131 includes a first primary winding 1311 and a first secondary winding 1312. The second transformer 132 includes a second primary winding 1321 and a second secondary winding 1322.
The first pulse output 111 is connected to gates of the first and third P-type transistors 1211, 1231. The second pulse output 112 is connected to gates of the first and third N-type transistors 1212, 1232. The third pulse output 113 is connected to gates of the second and fourth P-type transistors 1221, 1241. The fourth pulse output 114 is connected to gates of the second and fourth N-type transistors 1222, 1242.
Sources of the first, second, third, and fourth P-type transistors 1211, 1221, 1231, and 1241 are connected to the direct current input 125. Sources of the first, second, third, and fourth N-type transistors 1212, 1222, 1232, and 1242 are connected to ground.
One end of the first primary winding 1311 is connected to drains of the first P-type transistor 1211 and the first N-type transistor 1212, the other end of the first primary winding 1311 is connected to drains of the second P-type transistor 1221 and the second N-type transistor 1222 via the first capacitor 133 respectively.
One end of the second primary winding 1321 is connected to drains of the third P-type transistor 1231 and the third N-type transistor 1232, the other end of the second primary winding 1321 is connected to drains of the fourth P-type transistor 1241 and the fourth N-type transistor 1242 via the second capacitor 134, respectively. The first to fourth P-type transistors 1211, 1221, 1231, and 1241 and the first to fourth N-type transistors 1212, 1222, 1232, and 1242 are metal oxide semiconductor field effect transistors (MOSFETs). The first to fourth P-type transistors 1211, 1221, 1231, and 1241 and the first to fourth N-type transistors 1212, 1222, 1232, and 1242 are in on-states when high-level voltages are applied to the gates thereof, and are in off-states when low-level voltages are applied to the gates thereof. The high-level voltage can be a power voltage, and the low-level voltage can be a ground voltage.
Referring to FIG. 4, this shows schematic time charts of pulse signals provided by the PWM 110. In FIG. 4, VNA1, VNB1, VNA2, and VNB2 represent the pulse signals applied by the first, the second, the third, and the fourth pulse outputs 111, 112, 113, and 114, respectively. The pulse signals VNA1, VNB1, VNA2, and VNB2 have a same duty ratio of 50% and a same cycle period. The pulse signals VNA1 and VNA2 have a same phase, and the pulse signals VNB1 and VNB2 have a same phase. However, the pulse signals VNA1 and VNB1 have different phases. The difference of the phase of the pulse signal VNA1 and the phase of the pulse signal VNB1 is greater than 0, and not more than half the cycle period.
Working procedure and principle of the DC-AC converter 10 are described as follows, and for the simplicity, only one cycle period (t1˜t5) of the working procedure is described in detail.
During the period t1˜t2, the pulse signals VNA1 and VNA2 are low-level voltages, and the pulse signals VNB1 and VNB2 are high-level voltages. Thus, the first P-type transistor 1211 and the second N-type transistor 1222 are in on-states, while the second P-type transistor 1221 and the first N-type transistor 1212 remain in off-states. A direct current applied by the direct current input 125 is grounded via the first P-type transistor 1211, the first primary winding 1311, the first capacitor 133, and the second N-type transistor 1222. As a result, the first capacitor is charged and the first primary winding 1311 generates and stores electromagnetism energy therein. The first primary winding 1311 has a working current flowing in a clockwise direction therein.
The third P-type transistor 1231 and the fourth N-type transistor 1242 are switched on, while the third N-type transistor 1232 and the fourth P-type transistor 1241 are in off-states. The direct current applied by the direct current input 125 is grounded via the first P-type transistor 1231, the second primary winding 1321, the second capacitor 134, and the fourth N-type transistor 1242. As a result, the second capacitor 134 is charged, and the second primary winding 1321 generates and stores electromagnetism energy. The second primary winding 1321 has a working current flowing in a clockwise direction therein.
During the period t2˜t3, the pulse signals VNA1 and VNA2 jump to high-level voltages, and the pulse signals VNB1, VNB2 remain high-level voltages.
The first and second P-type transistors 1211, 1221 are in off-states, while the first and second N-type transistors 1212, 1222 are in on-states. The first N-type transistor 1212, the first primary winding 1311, the first capacitor 133, and the second N-type transistor 1222 cooperatively constitute a loop. The first primary winding 1311 releases the electromagnetism energy stored therein. The first capacitor 133 continues to be charged. The first working current flows clockwise in the first primary winding 1311. Moreover, the third and fourth P-type transistors 1231, 1241 are in off-states. The third and fourth N-type transistors 1232, 1242 are in on-states. The third N-type transistor 1232, the second primary winding 1321, the second capacitor 134, and the fourth N-type transistor 1242 cooperatively constitute a loop. The second primary winding 1321 releases the electromagnetism energy stored therein. The second capacitor 134 continues to be charged. The second primary winding 1321 has a working current flowing in the clockwise direction thereof.
During the period t3˜t4, the pulse signals VNA1 and VNA2 are high-level voltages, and the pulse signals VNB1 and VNB2 are low-level voltages. The first P-type transistor 1211 is in an off-state. The first N-type transistor 1212 is in an on-state. The second P-type transistor 1221 is in an on-state. The second N-type transistor 1222 is in an off-state. The direct current applied by the direct current input 125 is grounded via the second P-type transistor 1212, the first capacitor 133, the first primary winding 1311, and the first N-type transistor 1212. The first capacitor 133 is reversely charged. The first primary winding 1311 stores electromagnetism energy. The first primary winding 1311 has a working current flowing in a counterclockwise direction thereof.
The third P-type transistor 1231 is in an off-state, and the third N-type transistor 1232 is in an on-state. The fourth P-type transistor 1241 is in an on-state, and the fourth N-type transistor 1242 is in an off-state. The direct current applied by the direct current input 125 is grounded via the fourth N-type transistor 1242, the second capacitor 134, the second primary winding 1321, and the second N-type transistor 1222. The second capacitor 134 is reversely charged by the direct current applied by the direct current input 125. The second primary winding 1321 stores electromagnetism energy. The second primary winding 1321 has a working current flowing in a counterclockwise direction thereof.
During the period t4˜t5, the pulse signals VNA1, VNA2, VNB1, and VNB2 are all low-level voltages. The first and second P-type transistors 1311, 1221 are in on-states. The first and second N-type transistors 1212, 1222 are in off-states. The second P-type transistor 1221, the first capacitor 133, the first primary winding 1311, and the first P-type transistor 1211 constitute a loop. The first primary winding 1311 releases the electromagnetism stored therein. The first primary winding 1311 has a working current flowing in the counterclockwise direction thereof.
The third and fourth P-type transistors 1231, 1341 are in on-states, and the third and fourth N-type transistors 1232, 1242 are in off-states. The fourth P-type transistor 1241, the second capacitor 134, the second primary winding 1321, and the third P-type transistor 1231 constitute a loop. The second primary winding 1321 releases electromagnetism energy and the second capacitor 134 is changed. The second primary winding 1321 has a working current flowing in the counterclockwise direction thereof.
After the period t4 to t5, the DC-AC converter 10 works as repeating of the cycle t1 to t5. The first to fourth P-type transistors 1211˜1241 and the first to fourth N-type transistors 1212 to 1242 are switched between on and off states due to the driving of the pulse signals VNA1, VNA2, VNB1, and VNB2. Thus, the working currents in the first and second primary windings 1331, 1332 are switched between flowing clockwise and flowing counterclockwise, thereby generating corresponding alternating currents thereof.
The first pulse output 111 is connected to the first and third P-type transistors 1211, 1231. That is, the first and third P-type transistors 1211, 1231 are switched to on-states simultaneously.
Generally, a gate and a source of a typical transistor constitute a parasitic capacitor. Referring to FIG. 5, the gate and the source of the first P-type transistor 1211 constitute a parasitic capacitor C1, and the gate and the source of the third P-type transistor 1231 constitute a parasitic capacitor C2. Because the first and third P-type transistors 1211, 1231 are switched to on-states simultaneously, a parallel capacitance of the parasitic capacitors C1, C2 is a sum of the capacitance of the parasitic C1 plus the capacitance of the parasitic capacitor C2. Thus, a speed of response relating to the first and third P-type transistors 1211, 1231 being switched on simultaneously is declined comparing to what relating to each single one of the first and third P-type transistor 1211, 1231 being switched on separately. Accordingly, the first and third N-type transistors 1212, 1232, the second and fourth P-type transistors 1221, 1241, and the second and fourth N-type transistors 1222, 1242 are slow in response speed of switching between the on and off states, respectively.
What is needed, therefore, is a DC-AC converter that can overcome the above-described deficiencies.